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Holtek's new generation Touch Key Flash series MCUs are fully integrated with touch key functions, communication interfaces and display functions thus reducing greatly the need for external components. With the features of high S/N ratio touch switch control, power fluctuation rejection and excellent noise immunity, the stability of these touch keys has been greatly improved, thus offering solutions over traditional mechanical keys with their inherent weakness of rapid wear and tear and manufacturing complexity. These features combine to ensure effective and rapid product development in areas such as household appliances and other touch key controlled products.

Application Description Application Description

Question 1

Question 2

Question 3

Question 4

Question 5

Question 6

Question 7

Question 8

Question 9


Question 1

How is the 8-Bit TMR setup?

Answer

The 8-bit timer/counter is a count up timer which upon reaching a count of 255 (0FFH) will reset itself to 00H and generate an internal interrupt signal. To obtain different timer counts, say N, which is less than 256, the timer should be first preset with a fixed value of 256-N. After setting up this preset value, the timer should be activated which will enable it to count from this preset value to 255. The value that the timer is to count, N, is therefore given by the formula 256-(256-N) = N.

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Question 2

Is it acceptable to execute a CALL instruction during an interrupt service routine?

Answer

For the reason that the stack number in the BS83/84XXXA Flash devices is limited, care must be taken when executing the CALL instruction in an interrupt. If the stack is full when entering an interrupt, a stack overflow will occur if a CALL is executed which will corrupt the program flow and render an interrupt return unsuccessful. Therefore, using the CALL within an interrupt routine must be very carefully managed especially ensuring that spare stack levels are available.

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Question 3

Is it acceptable to allow a similar interrupt to occur when one is already being serviced?

Answer

Theoretically, when entering an interrupt routine the MCU will automatically clear the EMI flag (EMI=0), and forbid all other interrupts to be generated. If the EMI bit however is manually set high using the application program after the interrupt routine is entered, then any other interrupts (including the same interrupt) can be generated again when the stack is not full. To allow the same interrupt to be repeatedly generated, then care must be taken to backup data to prevent it being corrupted by subsequent interrupts. Generally, it is not recommended to allow another interrupt when an interrupt routine is entered except for an emergency condition.

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Question 4

How do I back up the interrupt data without using Push and Pop instructions?

Answer

Without Push and Pop instructions, designers can still assign special memory RAM Byte (ex. db ACCStack; for ACC Storage) to store data which may be corrupted during an interrupt. First save the ACC to a memory register and then use ACC to move the status register and other data to other data memory registers. Before returning from the interrupt, restore the backup data in reverse order and finally execute the RETI instruction to return to the main program.

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Question 5

What points should be noted when using the table read instruction?

Answer

There are two table read instructions. One is TABRDC for reading the table data in the present program memory page, and the other is TABRDL for reading data from the last page of the program memory. The Low Address of the table must be first written to the TBLP register before executing the table read instruction. The Low Byte Data of the table will be stored in the register assigned by the instruction while the High Byte Data will be stored in TBLH. Note that unused high address bits must be written as zero.

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Question 6

What is the different between the EEPROM data register, the special internal function register and the general registers?

Answer

The internal special function register uses direct addressing while the general registers can use either direct addressing or indirect addressing via the indirect pointer (MP0, MP1) for access. As for the EEPROM data register, which is quite different from the above two kinds, it needs to use the control register EECR (40H) in the BANK 1 to execute indirect addressing access.

For the EEPROM register description, refer to the BS83/84XXXA datasheet.

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Question 7

What is the data format for data transmission when accessing the internal EEPROM?

Answer

The data is MSB format, which means most significant bit first, for all transmission. Information, including Instruction Code, Address, Data, are all transmitted using MSB when an SK rising edge occurs (SK, serial clock signal).

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Question 8

How do I calculate the WDT time-out period?

Answer

WS2,WS1,WS0:WDTtime-out period selection
000:256/fLIRC
001:512/fLIRC
010:1024/fLIRC
011:2048/fLIRC
100:4096/fLIRC
101:8192/fLIRC
110:16384/fLIRC
111:32768/fLIRC
These three bits determine the division ratio of the Watch dog Timer source clock , which in turn determines the time out period.

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Question 9

What is the clock source for the WDT?

Answer

fLIRC°

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