Basic Information Functional Description Application Description Points to Note Others

Basic Information

Question 1

What are the contents of the HT48F I/O TYPE FLASH MCU with EEPROM range of devices?

Answer

The HT48F I/O TYPE FLASH MCU with EEPROM is supplied in Flash Memory capacities of 1K, 2K, 4K and 8K and EEPROM capacities of either, 128x8 or 256x8. Their part numbers are HT48F06E, HT48F10E, HT48F30E, HT48F50E and HT48F70E. For more details consult the relevant Data Sheet.

Question 2

What are the important features and characteristics of the HT48F I/O TYPE FLASH MCU with EEPROM device range?

Answer

Operating Voltage Range: 2.2V ~ 5.5V;
Industrial Specifications: -40°C ~ +85°C;
Low Voltage Reset Function
Flash Program Memory;
EEPROM data Memory;
For other information please consult the relevant Holtek Data Sheet.

Functional Description

Question 1

What is the operating frequency of the HT48F I/O TYPE FLASH MCU with EEPROM device series?

Answer

In principle when the MCU enters an interrupt routine, the EMI bit will be automatically cleared, which will disable other interrupts from taking place. However in the interrupt routine if the EMI bit is set high and if the Stack still has space, all other interrupts (including identical interrupts) will be executed. To enable identical interrupts, it is important to note that any backed up data must be carefully managed, to prevent it from being corrupted by the new interrupt. Unless it is an interrupt which is of immediate urgency, it is not recommended that interrupts are allowed to take place within other interrupts.

Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V

Question 2

How is indirect addressing used?

Answer

First write the Data Memory address to be read/write into the Memory Pointer. Then execute the required read/write function on the IAR register, e.g. MOV A, IAR. This will allow the data indicated by the Memory Pointer to be read. The Memory Pointer content is the address. Indirect addressing is particularly convenient for use for handling data arrays, first by placing the array address into the Memory Pointer after which the required data can be read back.

Question 3

During normal operation, how are read and write operations executed on the EEPROM in the HT48FXXE ?

Answer

During normal operation all operations to the EEPROM are conducted using the EECR register which is located at location 40H in Data Memory Bank 1.

By reading and writing to the EECR register, the EEPROM signal lines, CS, SK, DI and DO can be controlled. Software is used to control the EEPROM operation timing to implement EEPROM read and write operations. Control of the EEPROM data memory is executed using 7 instructions, READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL for which more details can be found in the datasheets.

Application Description

　

Question 1

When the program is within an interrupt handling routine, should other interrupts occur, can they be enabled ?

Answer

In principle when the MCU enters an interrupt routine, the EMI bit will be automatically cleared, which will disable other interrupts from taking place. However in the interrupt routine if the EMI bit is set high and if the Stack still has space, all other interrupts (including identical interrupts) will be executed. To enable identical interrupts, it is important to note that any backed up data must be carefully managed, to prevent it from being corrupted by the new interrupt. Unless it is an interrupt which is of immediate urgency, it is not recommended that interrupts are allowed to take place within other interrupts.

Question 2

As there are no Push or Pop instructions, how is interrupt information backed up ?

Answer

Although there are no Push or Pop instructions, the program can still point to certain areas of RAM to back up any data which might be corrupted by the interrupt handling program. First store the ACC to a byte of Data Memory, then use the ACC to transfer the STATUS register data and any other data to Data Memory. Reverse the process when returning from the interrupt routine to restore the backed up data, first restore other data, then the STATUS register and finally the ACC before executing a RETI instruction to return to the main program.

Question 3

How is the table instruction used and are there any special points to note ?

Answer

The table instructions have two kinds, one is the TABRDC instruction, which will read data from the same page of Program Memory that the statement is located. The second is the TABRDL instruction, which will only read data from the last page of the Program Memory. To read table data, the Low Address of the data location must be first placed into the TBLP register before executing the table read instruction. The Low Byte of the read back data will be placed into the chosen register specified in the table read instruction. The High Byte will be placed into the TBLH register. Any unused bits in the high byte data will be read as 0.

Question 4

When the WDT selects the WDT OSC as its clock, how is the Watchdog Timer timeout calculated ?

Answer

The WDT OSC at an operating voltage of 5V has a period of between 8ms and 33ms. The timeout period is calculated from the following formula: Clock Period x 2 ^(WS2~WS0) For example, if WS2~WS1 = 7, then the Watchdog Time timeout will be between, 8 ms x 128 = 1 sec and 33 ms x 128 = 4.2 sec

Question 5

When the MCU enters the Power Down mode, why does it still consume some current ?

Answer

When the MCU enters the Power Down mode, the system oscillator will be stopped, however the WDT oscillator (if the configuration options have enabled the WDT) and the RTC will continue to operate which will consume power. Additionally the conditions of the I/O pins will remain in the same condition as they were just before entering the Power Down mode which may also contribute to power being consumed.

Question 6

Is it possible to disable an external interrupt from generating a wake-up signal ?

Answer

Before entering the Power Down mode, if the EMI bit is cleared and then the EIF bit set high, then should an external interrupt occur it will not wake-up the MCU.

Question 7

If there are any unused I/O pins, how should they be managed?

Answer

If there are any floating I/O pins, then care should be taken as these pins can consume power. The best way to manage such pins is to have them setup as outputs. However if they must be setup as inputs then ensure that a pull-high resistor is connected, or if a pull-high resistor is not connected then connect these pins to ground.

Question 8

How are the two CLR WDT instructions used?

Answer

The two CLR WDT instructions can be used to increase the system reliability. If the program has two alternating loops, then the CLR WDT1 instruction can be placed in the first loop while the CLR WDT2 instruction can be located in the other loop. Once a program error occurs, or if the system encounters noise, which keeps it stuck in one of these loops, then the WDT will time-out and restart the system.

Question 9

When using the PA control register, PAC, why is it when the PA pin is written first with a 0 and then a 1, in the register window when examining the register why is no change seen?

Answer

When writing data to a specific bit in the PA data register, it is necessary to first clear the corresponding bit on the PA port control register PAC to zero, which means to setup the bit as an output. This is necessary to allow data to be written to the PA data register. Otherwise if the bit is setup as an input then the data register contents cannot be changed using software.

Question 10

What is the difference between selecting the WDT OSC or the fsys/4 as the WDT clock source?

Answer

If the WDT OSC is chosen as the WDT Clock Source, then should the system erroneously enter the Power Down Mode, the WDT Timer will continue to function, and when it times out, the system will be woken up. If fsys/4 clock is selected as the WDT Clock Source, then should the system erroneously enter the Power Down Mode, the clock will stop running and there will be no way for the WDT to wake up the system. However if using the WDT OSC there is a cost incurred, which is that this oscillator will increase slightly the power consumption of the device. For normal system operation, if the Power Down Mode is used normally, and if the Power Down Mode does not require a Watchdog Timer wake up function, then the WDT clock source can be chosen to be fsys/4.

Question 11

How is the 8-bit TMR setup?

Answer

The 8-bit Timer/Event Counter is a count-up counter, which will count up to a value of 255, which is 0FFH, at which point the counter will overflow and generate an interrupt. Therefore if it is required to count up to a number N, where N<255, the TMR register value must be setup to a value of 256-N. After setting up the TMR register value and starting the Timer/Event Counter, when it counts to a value of 255, on the next count, which is 256, it will overflow. Therefore the counted value will be 256-(256-N) = N.

Question 12

How is the 16-bit Timer/Event Counter setup and what is the order for reading?

Answer

The Data Bus of the series of HT48FxxE I/O Type FLASH MCU WITH EEPROM devices is 8-bits, therefore when reading or writing 16-bit data it has to be carried out in two operations. For write operations to the the 16-bit Timer/Event Counter, it is necessary to first write the low byte and then write the high byte. When reading, it is necessary to first read the high byte and then read the low byte.

Question 13

How is the 16-bit Timer value setup?

Answer

The 16-bit Timer/Event counter is a count up counter, which will count up to a value of 65535, which is 0FFFFH, after which it will overflow and generate an interrupt. If it is required to count up to a value N, where N<65536, then the value which must be placed into the timer’s registers is equal to 65536-N. After setting up the timer registers and starting the timer, the timer will count to a value of 65535, after which it will overflow on the next count, which is 65536. Therefore the counted value will be 65536-(65536-N) = N.

Question 14

PA is already low so why can it not wake up the MCU?

Answer

A wake up signal is instigated by a falling edge on the PA port. Therefore after entering the Power Down Mode if PA is already low and if it remains low during the Power Down Mode, because there is no falling edge no wake up signal will be generated.

Question 15

Why is it that when there is a falling edge on the external interrupt pin, no wake up is generated?

Answer

Although the MCU can be woken up by interrupts, the function is determined by the Interrupt Request Flag, EIF, transitioning from a 0 to a 1. When the MCU enters the Power Down Mode, if the EIF bit has already been set to 1, then any future transitions on the external interrupt pin will not wake up the MCU.

Question 16

In the HT-IDE3000 development system, in the Debug section of the Options menu, why is it not possible to select the Software Simulation Mode?

Answer

In the HT-IDE3000 development system, not all MCU devices have software simulation functions. The HT48FXX series presently does not have this function.

Question 17

The HT48FXX series of MCUs have two Data Memory banks, Bank 0 and Bank 1. If it is required to execute operations on the Data Memory, how can the bank selection be determined?

Answer

In the HT48FXX series of MCUs, the value of the Bank Pointer, BP, determines which bank is read or written to. If BP is equal to 0, then the Data Memory Bank 0 is selected, if BP is equal to 1, then Bank 1 is selected. It is important to note that when reading or writing to Ban 1, the Memory Pointer MP1, must be used to indirectly address this bank, any other addressing methods will have no effect.

Question 18

Is it possible to implement a CALL within an Interrupt Service Routine?

Answer

Because the number of stack levels within the HT48FxxE devices are limited, when implementing a CALL within an Interrupt Service Routine, there are some points to note. If the stack is already full, then this will result in a Stack Overflow and the program will not properly return. For this reason if a CALL has to be implemented within an interrupt, it is important to consider the worst case scenario for the number of used Stack Levels, and ensure that there are free stack levels in the interrupt routine before the CALL instruction is executed.

Question 19

When the RC oscillator is selected as the system clock, what is the purpose of the external capacitor connected to the OSC1 pin? Can this capacitor be omitted?

Answer

The external capacitor connected to the OSC1 pin is to prevent any crossover interference from the OSC2 pin and allow the OSC2 pin to generate a stable 1/4 clock frequency output. If however the OSC2 output is not used, then it is not necessary to add the capacitor.

Question 20

When using the external RC oscillator, how can the frequency accuracy be determined?

Answer

The external RC circuit is connected to the OSC1 pin and the OSC2 pin is a floating output. The frequency of the internal RC oscillator can be measured on pin OSC2 with an oscilloscope. The frequency measured will be Fsys/4.

Question 21

Regarding the buzzer function, when using this function and choosing the I/O as a PFD output, BZ_BZB, after connecting up the circuit and checking for errors, and after setting the I/O pins as outputs, why does it not work?

Answer

The device uses the Timer/Event Counter PFD to generate suitable frequencies to drive an external buzzer. Therefore check that the Timer/Event Counter output is correctly enabled, and also check that the PFD output frequency is in fact a correct audio frequency suitable to drive the buzzer. The frequency can be calculated from the following formula:
Fint/[2x(256-N)]
Fint is the frequency of the Timer/Event Counter generated overflow interrupt, and N is the initial value placed into the Timer/Event Counter register.

Question 22

The HT48F06E has an internal PFD, Programmable Frequency Divider, function which can drive external buzzer; how is it used?

Answer

The buzzer pins BZ and /BZ are pin-shared with the I/O pins PB0 and PB1. If the pins are to be used with the internal PFD function to drive an external buzzer, then the two pins of the passive type buzzer should be connected to the BZ and /BZ pins. In the configuration options the Output Type PB0-PB1 option should be selected to choose the PFD BZ_BZB. The frequency setup by the Timer/Event Counter to generate the PFD frequency is the frequency for the external buzzer. When being used the Timer/Event Counter output should be enabled. When the PB0 is set to 1, then the buzzer will generate sounds, when cleared to 0, the buzzer will be off.

Question 23

Are there differences between using the READ instruction for the EEPROM in the HT48F06E/10E/30E and the HT48F50E/70E?

Answer

There are differences. The READ instruction is used to read one or more bytes of data from the EEPROM. To execute a READ instruction the CS bit must be first set high and kept high, then a start “1” bit followed by a “10” must be transmitted on the DI pin. After this the address signal, MSB first, is transmitted. For the 128 x 8 bit HT48F06E/10E/30E EEPROM, there is a 7-bit address and for the 128 x 8 bit EEPROM there is a 9-bit address. A null bit must be inserted between the instruction code and the address MSB. After transmitting the A0 bit, the data can be read, MSB first on the rising edge of SK on the DO pin. This is shown on the accompanying timing diagram.


Question 24

What is the difference in method between accessing data from the EEPROM data registers and accessing data from the special function and normal registers?

Answer

Accessing data from the special function registers is done using direct addressing. Accessing data from the normal registers can also use direct addressing or by using the memory pointers, MP0 and MP1, can use an indirect addressing method. For the EEPROM data registers, accessing data is different from the above two methods. This requires using the Bank 1 EECR register to execute indirect addressing.
Accessing the EEPROM data register using the EECR register to write data, the transfer of which is conducted on a 3-line interface. The instructions used include the following seven: READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL. For further details regarding these seven instructions consult the relevant specification.

Question 25

During program writing, to construct a table in the Program Memory, how is an absolute address setup? If it is not suitable to use ORG are there other methods?

Answer

The ORG expression is directed at the present section start address offset and is not an absolute address, therefore SECTION can be used to construct a Table with absolute addresses, for example:
Table .section at 300 'code' can place the following Table start address at the absolute value of 300.

Question 26

When accessing the internal EEPROM, what is the data format for data transmission?

Answer

Data transmission should be handled in MSB format. All information whether Instruction Code, Address or Data is all transmitted in MSB format when the SK line goes high. SK is the serial clock signal.

Points to Note

Question 1

When the MCU is powered-on, what are the limitations on the VDD rise time?

Answer

When the MCU is powered-on, for the reset to function properly, it is recommended that the power on VDD rise time should be limited to less than 20ms. If the VDD rise time exceeds this time the internal reset may not function properly.


Question 2

When programming using C language for the HT48R10A-1, why is it when changing to use the HT48F10E device, the required Program Memory capacity increases?

Answer

This is because the Data Memory in the HT48R10A-1 only has one bank, and when reading or writing to the Data Memory it is not required to use a Bank Pointer for control. However the HT48F10E has two banks, and when compiling to generate the source ASM code, and addressing the Data Memory, it will automatically add code to control the Bank Pointer. As a result the amount of code generated during compilation will increase.

Question 3

For the HT46F4xE, Flash Type MCU with EEPROM device, are there any special points to note when using?

Answer

The following points should be noted for the EEPROM in the HT46F4xE:
1. The two SCL and SDA lines are not used for read/write control. The EEPROM control register EECR is used for this function.
2. The EEPROM data cannot be directly accessed by other ICs, only the HT46F4xE can be used for direct access. The reason is because the EEPROM has no external communication port.
3. Using indirect addressing the EEPROM signals CS, SK, DI and DO are controlled using the EECR register in Bank 1 using software to implement read and write data functions to the EEPROM
4. EEPROM operations are executed using the seven READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL instructions. For more information on the protocol for these instructions and on the EEPROM, the HT46F4xE datasheet should be consulted..

Question 4

For the HT48F series devices there are 7 instructions for reading and writing data to the internal EEPROM Data Memory, namely: READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL. Can these 7 instructions be directly used as are the other 63 instructions?

Answer

This is not possible. The 63 instructions in the instruction set are executed in one or two instruction cycles. Data access to the EEPROM in the HT48F series devices is carried out in a serial way. These 7 instructions are all carried out in a specific way which must be adhered to for correct operation.


Others

Question 1

When using the ICP programmer with the HT48FXXE, what pins are used?

Answer

The HT48FXXE ICP programmer in total uses 5 pins, these are VSS, VDD, RESET, SDATA (PA0) and SCLK (PA4).