Basic Information Functional Description Application Description Points to Note Others

Basic Information

 

Question 1

What operating modes do the CTM provide?

Answer

The CTM(easy type TM) provides the following operating modes:
Compare match mode
Timer/Event counter mode
PWM mode

Question 2

How can I read/write data to the EEPROM? For how long can the Data be retained? How many times can I write data?

Answer

  • Data EEPROM method of read/writing is as follows:
    Three registers are relevant to the Data EEPROM which are EEA, EED and EEC.
    The EEA is the address register.
    The EED is the data register.
    The EEC is the control register.

  • Read Operation:
    Write the address that you want to read into the EEA register, set the REDN bit (EEC.1) as 1, (here note that the EEC register is located in Bank 1, when using assembly language, first set BP = 1 before writing). Then set the RD bit (EEC.0) also to 1. The MCU will then execute a read operation to the assigned address and start to detect the RD (EEC.0) bit. When the RD bit value changes from 1 to 0, this means that the read operation has been completed and the read data result will be saved in the EED register.

  • Write Operation:
    Write the desired address into the EEA register, and the data value to the EED. Then set the WREN bit (EEC.3) to 1 and the WR bit (EEC.2) also to 1. The MCU will execute a write function to the assigned address, and then detect the WR (EEC.2) bit. When the WR value changes from 1 to 0, the write operation is completed. Note that as the EEC resister is located is Bank1, when using assembly language first set BP = 1 before writing.

    • The EEPROM data retention time is greater than 10 years.

    • Up to 1,000,000 EEPROM write cycles are possible.

    • Setting the RDEN, RD, WREN and WR bits to 1 at the same time is allowed for both EEPROM read and write operations.

Question 3

Which writer is used for the HT66Fx0?

Answer

To program the HT66Fx0 series, use the e-Writer with the HOPE3000 software.

Question 4

When the high frequency clock is set as an external 4MHz crystal oscillator and the CTM is in the PWM mode, how long is the PWM cycle if controlled by the CCRP?

Answer

When the high frequency clock (fH) is set up as an external 4MHz, if the CTM clock is chosen as fH/16, the PWM cycle controlled by the CCRP may have eight possibilities as follows.

If the CTM clock cycle is 4MHz/16=250KHz, one clock cycle will be 4us.
When the CCRP value is set as 000, the PWM cycle will be 4us*1024=4096us=4.096ms.
When the CCRP value is set as 111, the PWM cycle will be 4us*896=3584us=3.584ms.
When the CCRP value is set as 110, the PWM cycle will be 4us*768=3072us=3.072ms.
When the CCRP value is set as 101, the PWM cycle will be 4us*640=2560us=2.56ms.
When the CCRP value is set as 100, the PWM cycle will be 4us*512=2048us=2.084ms.
When the CCRP value is set as 011, the PWM cycle will be 4us*384=1536us=1.536ms.
When the CCRP value is set as 010, the PWM cycle will be 4us*256=1024us=1.024ms.
When the CCRP value is set as 001, the PWM cycle will be 4us*128=512us=0.512ms.

Question 5

When the high frequency clock is set as an external 4MHz crystal oscillator and the CTM is in the PWM mode, how long is the PWM cycle if controlled by the CCRA?

Answer

When the high frequency clock is set as the external 4MHz, if the CTM clock is chosen as fH/16, the CTM clock cycle will be 4MHz/16=250KHz and one clock cycle will be 4us. The PWM cycle will be the CCRA value x 4us.
When the high frequency clock is set as the external 4MHz, if the CTM clock is chosen as fH/64, the CTM clock cycle will be 4MHz/64=62.5KHz and one clock cycle will be 16us. The PWM cycle will be the CCRA value x 16us or namely the CCRA value x clock cycle.

Question 6

What is the TM I/O pin status in the HT66F40?

Answer

The HT66F40 has three TMs in total, a compact type CTM, a standard type STM and an enhanced type ETM.
The number of TM output pins are:
CTM: has 2 outputs named TP0_0 or TP0_1.
Note: TP0_0 or TP0_1 only provide the CTM with an output pin selection. The CTM only has a single channel output function.
STM: has 2 outputs named TP2_0 or TP2_1.
For the STM in the PWM or single pulse mode, TP2_0 or TP2_1 can be setup as output pins.
Note: TP2_0 or TP2_1 only provide the STM with an output pin selection. The STM only has a single channel output function.
ETM: has 4 outputs named TP1B_0/TP1B_1/TP1B_2/TP1A.
In the PWM or single pulse mode, the ETM can provide a two channel PWM or single pulse output (TP1A/TP1B). The first channel is the output from TPA1 and the second channel may be output from either TP1B_0, TP1B_1 or from TP1B_2.

The number of TM input pins are:
CTM: has 1 input named TCK0, used as the CTM external clock input. The CTM has no capture mode.
STM: has 1 input named TCK2, used as the STM external clock input.
Additionally, for the ETM in the capture input mode, TP2_0 or TP2_1 can be setup as the input pin for signal detection.
ETM: has 1 input named TCK1, used as the external clock input.
Additionally, for the ETM in the capture input mode, TP1A can be setup as an input pin for signal detection on the first channel. Either TP1B_1 or TP1B_2 can be chosen as the input pin for signal detection on the second channel.
The TM pins are shared with the other functions. Each pin setup can be selected using three registers, PRM0, PRM1 or PRM2.

Question 7

What functions do the comparators provide and how are they setup?

Answer

1. Hysteresis Control Function:
These functions can prevent noise from creating comparator malfunctions.
2. Input pin shared with I/O function:
When the CxSEL bit is set to 1, the I/O pin will be setup as a comparator input instead of as a common I/O port.
3. Comparator output option function:
Each comparator output has a corresponding register bit which can also be transmitted to an external I/O pin. The output pin choice is selected using a configuration option.
4. Comparator ON/OFF function:
The comparator has an ON/OFF switch that can be used to save power when the function is not being used.
5. Polarity Transfer Function:
The output logic voltage of the comparator can be chosen using an internal register bit.
6. Interrupt Function:
When either of the two comparators change state, their corresponding interrupt flag will be set. If the interrupt condition is satisfied, it will jump to the corresponding interrupt address to execute the interrupt service program.
7. Wake Up Function:
In the Power Down Mode, if the comparator generates an interrupt the MCU will be woken up.
If the wake-up function is not required in the Power Down Mode, set the register interrupt request flag to 1 before power-down.


* Setup the functions:
1. Hysteresis Control Setting:
Set the CxHYEN bit in the CPxC control register to 1 to enable the hysteresis control function to prevent noise from causing comparator malfunctions.
2. Input pin shared with I/O option setting:
Set the CxSEL bit in the CPxC control register to 1. Therefore the common register bit and I/O will be used as a comparator input.
Clear the CxSEL bit in the CPxC control register to 0. Therefore the common register bit and I/O will be used as an I/O pin.
3. The Comparator Output Selection Setting:
When a comparator reset occurs, the following settings can be used to decide if the register needs to output to the external I/O.
Clear the CxOS bit in the CPxC control register to 0 and CxSEL to 1. Therefore the comparator output will be reflected in the CxOUT bit and on the external pin.
Set the CxOS bit in the CPxC control register to 1, therefore the comparator output will only be reflected in the internal register and not on the output pin.
4. Output polarity selection:
The logical voltage from the CxPOL bit in the CPxC control register and the comparator input pins will determine the comparator logical output. Taking comparator 1 as an example:
C1POL=0
0: C1+ < C1-
1: C1+ > C1-
C1POL=1
0: C1+ > C1-
1: C1+ < C1-

Question 8

What is the accuracy of the 12-bit A/D? How long is the sampling time? What is the conversion speed?

Answer

  • The 12-bit A/D accuracy is 10 bits (12 bits+/-2 bits.)

  • The A/D sampling time is tADCS =4 tAD
    In which tADCS is the sampling time and tAD the ADC clock. To ensure A/D conversion accuracy tAD should not be less than 0.5us.
    For example: if the system frequency is 4MHz, the ADC clock is fSYS /2 (2MHz) and then the ADC clock cycle tAD will be 0.5us. In that condition the A/D sampling time will be tADCS =4 tAD =4*0.5us=2us.

  • The A/D transfer speed is : tADC = 16* tAD
    For example: if the system frequency is 4MHz, the ADC clock is fSYS /2 (2MHz). Then the ADC clock cycle tAD will be 0.5us of 12 bits and then in that condition the A/D sampling time will be tADCS =16*0.5us=8us.

Question 9

What is the internal equivalent circuit of the 12-bit A/D? What are the resistor and capacitor values?

Answer

The 12-bit A/D internal equivalent circuit is shown below:

Signal Description:
VA: external analog signal source
Rs: external analog signal output impedence
PortPin: analog signal input pin
CPIN: analog signal input pin capacitor, CPIN = 5pF
two diodes: the protective diode on the PAD, VT=0.6V
SS: analog signal sampling switch
RSS: analog signal sampling switch equivalent impedance of about 1.4KΩ
Csample: sampling hold capacitor; value is 43pF

Question 10

What is the tolerance of the ERC Oscillator? What will the effects of temperature be?

Answer

The external resister oscillator (ERC) tolerance changes with both voltage and temperature. For details refer to the test values below or to the datasheet for actual information.

The external resister tolerance will also affect the fERC, therefore it is recommended to use precision type resistors.

Question 11

What is the tolerance of the internal HIRC OSC? What will the effect of temperature be? What frequencies can be chosen?

Answer

The internal HIRC oscillator frequency will vary with voltage and temperature. Check the table below for reference or the datasheet for actual information. The internal HIRC frequency can be selected from the configuration options to be either 4MHz, 8MHz or 12MHz and the operating voltage should be either 3V or 5V.

Question 12

Which ICE is used for HT66Fx0? Can it be used with other devices?

Answer

The E-ICE can be used with the New Flash MCU but note that the daughter board needs to be changed.
IDE3000 V7.1 or higher versions can be used for development.

Question 13

How do I use the Pin-Remapping function?

Answer

The I/O function options are implemented by three registers, PRM0, PRM1 and PRM2 whose value will all be 00H after a power on reset. For different part numbers, the number of the PRMX registers will be different. For detail register definition please refer to data sheet.
EX：PCKPS (PRM0.0)
PCKPS=0： PCK on PC2，PINTB on PC3;
PCKPS=1： PCK on PC5，PINTB on PC4;

Question 14

What is the maximum and minimum overflow time of the WDT?

Answer

If the WDT clock fs is 32KHz:
If the prescaler is set to a maximum value of 2^15, then the WDT overflow cycle will be about (1/32KHz)*(2^15)=1S
If the prescaler is set to a minimum value of 2^8, then WDT overflow cycle will be about (1/32KHz)*(2^8)=8ms
If other clock sources are used, then the WDT times can be similarly calculated.

Question 15

How many WDT Configuration Option are there?

Answer

The WDT Configuration Options are:

  • WDT on/off option: Enable/Disable
  • WDT Clock Selection: fsub / fsys/4
  • WDT clear instruction option: 2 instructions or 1instruction

Question 16

What is the wake-up time for each oscillator woken up from Sleep or Idle Mode?

Answer

The wake-up times for the different oscillators to wake-up from the Sleep or Idle Mode are shown in the table:

When woken up from the Sleep1 or Idle0 Mode, if the HXT has been selected as the system clock for the Normal Mode and the fast wake-up function is enabled, it takes one or two Tsub clock cycles of the LIRC or LXT oscillator to wake up the system. The system will firstly use the Fsub as the clock source and after 1024 HTXT clock cycles, the HTO flag will be set as 1 to switch the system operation to the HXT oscillator.

  • It is not necessary to use the fast wake-up function if waking up from other modes. For detailed wake-up times please refer to the table.
  • If the system frequency HXT=4MHz, when FSTEN=0, it takes 1024*(1/4)=256us to wake up from Sleep0, Sleep1 and Idle0 Mode, and 1*(1/4)=0.25us to 2*(1/4)=0.5us from the Idle1 Mode. When the system frequency is the ERC or the 4MHz at a frequency of 4MHz, then from then it takes 15*(1/4)=3.75us to 16*(1/4)=4us to wake-up from the Sleep0, Sleep1 or IDLE0 Modes and 1*(1/4)=0.25us to 2*(1/4)=0.5us to wake-up from the IDLE1 Mode.

Question 17

What is the ON/OFF status of the different clock signals in the different operating modes?

Answer

Different clocks have different ON/OFF situations in the Normal, Slow, Idle or Sleep mode. For details refer to the following figure and table.

Question 18

What operating modes are provided by the STM?

Answer

The STM (Standard TM) provides the following operating modes:

  • Compare match mode
  • Timer/counter mode
  • PWM output mode
  • Single pulse output mode
  • Input capture mode

Question 19

What operating modes are provided by the ETM?

Answer

The ETM (enhanced TM) provides the following operating modes:

  • Compare match mode.
  • Timer/counter mode.
  • PWM output mode
  • Single pulse output mode
  • Input capture mode

Question 20

How do I program the memory in the HT66F40?

Answer

The HT66F40 writer connects to the MCU as shown below, using the HOPE3000+E-Writer to program.

Functional Description

 

Question 1

How does the STM interpret an inactive and active level in the PWM mode?

Answer

In the PWM mode, if the initial value of the STM pin is Low and the PWM pin is Active High, the PWM output waveform will be:

A high voltage is the Active Level and a low voltage is the Inactive Level.
In another case, in the PWM mode, if the initial value of the STM output pin is High and the PWM output is Active Low, the PWM waveform will be:

A low voltage is the Active Level and the a voltage is the Inactive Level.
Therefore, both the active level and inactive level are connected with the initial value.

Question 2

What is the purpose of the two control bits, TnIO1 and TnIO0, in the STM of the HT66F40?

Answer

The T2IO1 and T2IO0 bits have different functions depending upon the mode.

  • In the Compare Match Mode: they are used to select the output logic voltage.
    When T2IO1/T2IO0=00 and a compare match occurs, the output voltage of the STM output pin will not change.
    When T2IO1/T2IO0=01 and a compare match occurs, the STM output pin will send out a low voltage.
    When T2IO1/T2IO0=10 and a compare match occurs, the STM output pin will send out a high voltage.
    When T2IO1/T2IO0=11 and a compare match occurs, the STM output pin will toggle its value.

  • In the PWM and single pulse mode:
    When T2IO1/T2IO0=00 and is in the PWM mode, the STM output pin will output an Inactive Level.
    When T2IO1/T2IO0=01 and is in the PWM mode, the STM output pin will output an Active Level.
    When T2IO1/T2IO0=10 and is in the PWM mode, the STM output pin will output a PWM signal.
    When T2IO1/T2IO0=11, the PWM Mode will switch to the single pulse mode.

  • In the input signal capture mode:
    When T2IO1/T2IO0=00 and is in the input signal capture mode, if an STM input signal rising edge occurs, the internal counter value will be sent to the CCRA to be saved and an STM interrupt will be generated.
    When T2IO1/T2IO0=01 and is in the input signal capture mode, if an STM input signal falling edge occurs, the internal counter value will be sent to the CCRA to be saved and an STM interrupt will be generated.
    When T2IO1/T2IO0=10 and is in the input signal capture mode, if either a STM input rising or falling edge occurs, all the internal counter values will be sent to CCRA to be saved and an STM interrupt will be generated.
    When T2IO1/T2IO0=11, the input signal capture function will be disabled.

Question 3

What does Edge Alignment mean?

Answer

Edge Alignment uses single directional counting that will clear the main counter to zero when its value rises to match the value in the CCRP. In the Edge Alignment Mode, when the main counter is cleared to zero, the PWM leading edge signal is generated, which is used for high power control.
See the below fig. for reference.

Question 4

What is Centre Alignment?

Answer

Centre Alignment uses dual directional counting. The main counter starts by counting up and when the counter reaches a value to match the value in CCRP or CCRA (If TnCCLR=0, then CCRP will be matched; If TnCCLR=1, then CCRA will be matched) the main counter will then start to count down, and change back again to count up when the counter value has decreased to zero. In the single directional counting Mode, when the main counter is matched with the CCRP or CCRA value, the counter will be directly reset from its value to zero along with an I/O transition on the TM I/O pin same time which is very suitable for low power control applications. When in this dual directional counting mode, when the main counter matches the CCRP or CCRA value, it will not be reset directly to 0 from its maximum value but rather just start decrementing. In this way the MCU transient currents are less. See the figure shown below.

Question 5

What is the priority of the multi-function pins?

Answer

For the multi-function pins, some points regarding priority must be noted:

  • Input Pins
    In the beginning, the ADC and register input have the highest priority. If the ADC is enabled, only the ADC input is effective. Other functions on the same pin, either input or output will be ignored except for the comparator input. When the ADC is disabled, the other input functions can be used with this pin at the same time.
    Example: For the PA2/TCK0/C0+/AN2 pin which has four functions, all functions are inputs. If all these functions are enabled, which means PA2 will be an input, the TMR0 input is enabled, the ADC is enabled and the comparator input pin C0+ is enabled. Here only the ADC input will be effective while the other inputs will be disabled.
  • Output Pins
    When setup as output functions, the common pin priority is from left to right. Taking the PA5/C1X/SDO/AN5 pin as an example, when all outputs are enabled, then SDO has priority.

Question 6

What are the WDT functions used for?

Answer

The WDT function is to prevent malfunctions or to prevent the program jumping to unknown addresses due to external causes, such as ESD, noise etc. This will prevent the WDT clear instruction from being executed and result in a system reset due to the WDT overflow.

Question 7

How do I enable/disable the WDT?

Answer

The WDT has dual control using a configuration option and the WDTEN3~WDTEN0 bits in the WDTC register. The WDT is disabled only when the WDT Disable is selected from the configuration option and the WDTEN3~0 bits are set to 1010b. When the WDT Enable is selected or when the WDTEN3~0 bits have any other value, then the WDT will not be disabled.

Question 8

What difference does it make to a WDT overflow when the program operates in the Normal/Slow mode and in the IDLE or Sleep mode?

Answer

The main effect is on the registers. When in the Normal/Slow mode, if a WDT overflow occurs, most registers with special functions will be reset. In the IDLE or Sleep mode, if a WDT overflow occurs, the values of most registers will not change. For detailed information refer to the datasheet. Additionally, both conditions will generate a device reset and reset the Program Counter to 0000H. This means that the program will continue execution from the first instruction. If TO=1 (STATUS.5) and PDF=1 (STATUS.4), then the WDT overflow has been generated from the IDLE or Sleep Mode. If TO=1 and PDF=u, then the WDT overflow has been generated from the Normal/Slow mode.

Question 9

How many methods are there to clear the WDT?

Answer

There are three methods to clear the value in the WDT counter:
1. Reset the system; this includes an external Reset pin reset, an LVR Reset, a WDT Reset, a Power-on Reset etc.
2. Clear using software instruction, which is CLR WDT or CLR WDT1 and CLR WDT2
3. Use a HALT instruction

Question 10

What is the function of the Fast Wake-up? Are their any special points to note and how is it setup?

Answer

In order to reduce power consumption, the device may enter the Idle0 Mode or Sleep Mode which will disable the high frequency system oscillator. When the device has woken up, a certain amount of time is required for the high speed oscillator to start up and stabilise, to ensure normal operation. For quick normal operation after a wake-up, the Fsub, the LXT or LIRC oscillator, can be used as a temporary clock to drive the system until such time as the high speed oscillator has stabilised. Whether the Fsub clock is sourced from LXT or LIRC can be selected using the Configuration Options.
Are there any special points to note when using the Fast Wake-up function?

  • The fast wake-up clock source is the WDT clock. For a fast wake-up operation, the WDT must be enabled. The fast wake-up function can be enabled or disabled using the FSETN bit in the SMOD register.
  • Due to the WDT clock requirements, the fast wake-up function can be executed only when HXT is chosen as the system clock in the Normal Mode and is operated in the Idle0 Mode and Sleep1 Mode.
How is the fast wake-up function setup?
  • If the HXT is chosen as the system clock for the Normal Mode and the fast wake-up function is enabled then it will require one or two Fsub clock cycles of the LIRC or LXT oscillator to wake up the system. After these one or two clock cycles, the Fsub clock will be temporarily used as the clock source. The HTO flag will then be set high after 1024 HXT clock cycles have elapsed after which time the system will switch to operating with the HXT oscillator.
    The specific setup steps are as follows.
    1. High Speed System Oscillator Selection – fH: choose HXT as the system clock
    2. Low Speed System Oscillator Selection – fL: choose LXT or LIRC as the Fsub source
    3. Watchdog Timer Function: choose Enable or set the WDTEN0~WDTEN3 bits in the WDTC register to any value except 1010 to enable the Watchdog Timer Function
    4. WDT Clock Selection – fs: choose Fsub to enable the Fsub
    5. Set the FSTEN bit in the SMOD register to 1 to enable the Fast Wake-up function
    6. After the device has woken up, check if the HTO bit value in the SMOD register is 1 to determine if the system has switched to the HTX oscillator. If the HTO bit is still 0, then the high speed clock is not yet being used as the system clock.
  • If the system clock is using the ERC or HIRC oscillator, it will take 15~16 ERC or HIRC clock cycles in the Sleep or Idle0 Mode for the system to wake-up and operate normally. In this condition the FSTEN bit has no influence as the fast wake-up function is note required.
  • If the system clock is using the LIRC oscillator, it will take 1~2 LIRC clock cycles from the Sleep or Idle Mode to wake up the system and start operating normally. In this condition the FSTEN bit has no influence as the fast wake-up function is not required.

Question 11

How long does it take the system to stabilise from a power-down condition to Wake-up when using the external crystal as the system oscillator?

Answer

If an external crystal is used as the high frequency system clock and the fast wake-up function is enabled, then just after the system is woken up, and after one or two LIRC clock cycles have elapsed, the system will firstly operate with the LIRC oscillator for 1024 high frequency clock cycles. At this point the HTO flag will be set to 1, and then the system will switch to the external crystal oscillator.
As an example, taking LIRC as 32KHz and the system clock as a 4MHz crystal oscillator; then one LIRC clock cycle is 31.25us while two cycles will be 62.5us. The stabilisation time for the oscillator plus 1024 high frequency cycle time is about 1~2ms. Therefore it will take 1~2ms+62.5us for the system to stabilise after wake-up and start normal operation with the high frequency oscillator.

Question 12

How long does it take for the system to stabilise from a power-down condition to Wake-up when using the ERC or HIRC as the system oscillator?

Answer

If the ERC or HIRC is used as the high frequency system clock, it is not necessary to enable the fast wake-up function. The system needs 15~16 ERC or HIRC cycles after a wake-up before the HTO flag is set to 1 for the system clock to be switched to ERC or HIRC. As an example, if the system oscillator is a 4MHz HIRC, then the clock period be 0.25us. The HIRC system oscillator therefore needs 16 x 0.25us which is equal to 4us after a wake-up to stabilise and then begin normal operation.

Question 13

How do I use the table read instruction in the HT66F40?

Answer

The table read pointers of the HT66F40 are TBHP and TBLP. Set the table read pointer value before using the table read instruction TABRD to read the data. It takes 2 machine cycles to execute the TABRD instruction. High byte data read by TABRD will be saved to the TBLH register while low byte data will be saved to a user defined register. See the program below for reference.
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer
mov tblp,a
mov a,07h ; initialise high table pointer
tbhp,a
:
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address _706H_ transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address _705H_ transferred to tempreg2 and TBLH in this
; example the data _1AH_ is transferred to tempreg1 and data _0FH_ to
; register tempreg2
:
:
org 700h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00FH, 01Ah, 01Bh

Question 14

For the HT66F40, when the TnON bit changes from low to high, what will be affected?

Answer

1. The TM main counter will be cleared to 0.
2. The TM output pin will be reset to its initial logic status.


Note: In the above table, only one of the HXT/ERC/HIRC clock sources can be selected at the same time, as is the case for the LIRC/LXT clock sources.

Question 15

What is the difference between a TM counter and a general counter?

Answer

The TM counter provides functions such as timer counter, input capture, compare match output, PWM, single pulse output etc. When compared with a general timer its features are far more extensive, such as combined PWM control and Timer function for more flexible control.
There are three types of TM counters, CTM, STM and ETM, namely Compact type TM, Standard type TM and Enhanced type TM. Features provided are as follows:

  • For normal counters, the value can be set from any value to the overflow value to generate an interrupt. The TM counter always starts from 0 and an interrupt will occur when the counter value is the same as that of the compare register value or when the counter overflows.
  • The TM counter contains a PAUSE bit to provide a stop function to stop counting at any time. For general counters, this can only be done by disabling the timer.
  • The CTM and STM have the same counting methods as the general counter as they are all count up types, however the ETM has the option of either count-up or count-down.

 

Application Description

 

Question 1

What functions does the LCD COM PORT provide and how is it used?

Answer

  • The LCD COM port shares the same pins with PC. When used as an LCD COM port, a 1/2 VDD bias voltage can be generated.
  • When used as an LCD COM port, the SCOMEN and COMnEN bits in the SCOMC register should be set to 1, as shown in the following table.

Question 2

How do I use the CTM to produce a 100us interrupt?

Answer

Take the HT66F40 for example:

  • Firstly set the T0M1/T0M0 bits in TM0C1 to 11, namely place the CTM in the timer/counter mode.
  • Set the T0CCLR bit to 1. When the main counter matches the CCRA value, the counter will reset and generate a T0AF interrupt.
  • Set the high frequency clock as the external 4MHz crystal oscillator by selecting fH as XTAL from the configuration options.
    Set the T0CK2~T0CK0 bits in TM0C0 to 010. Setup the CTM clock as fH/16, namely 4MHz/16=250KHz with a 4us system clock cycle.
  • Set the TM0AH/TM0AL value to 25. When the CTM value (TM0DH/TM0DL) and TM0AH/TM0AL matches and generates a CCRA interrupt, the CTM will generate a 100us interrupt.
  • Enable the EMI, the CCRA interrupt enable bit and T0AE, and the corresponding multi-function interrupt bit MF0E.
  • Enable the timer/counter for timer operation. When the T0ON bit changes from low to high, the timer/counter (TM0DH/TM0DL) value will be cleared to 00 automatically.
  • The CTM starts counting from 0. After 25 clocks the value will be the same as the CCRA register value (TM0AH/TM0AL), then a timer/counter interrupt will be generated with a period of 25x4us=100us.

Question 3

How do I output a 1:1 duty cycle square waveform with a period of 200us at the CTM pin? It is required that the initial value of the square wave is low.

Answer

Taking the HT66F40 as an example:

  • Firstly set the T0M1/T0M0 bits in TM0C1 to 00, namely the CTM is setup in the compare match mode.
  • Set the T0IO1/T0IO0 bits TM0C1 to 11. The CTM output pin will be a toggle type output.
  • Set the T0OC bit in TIM0C1 to 0, then the initial value of the CTM output pin will be a low level.
  • Set the T0CCLR bit to 1. When the main counter value matches the CCRA value, the main counter will be cleared to 0 and generate a T0AF interrupt.
  • Set the high frequency clock as the external 4MHz crystal oscillator by selecting fH as a XTAL from the configuration options.
    Set the T0CK2~T0CK0 of the TM0C0 as 010 to enable the CTM clock as fH/16, namely 4MHz/16=250KHz with a 4us system clock cycle.
  • Set the TM0AH/TM0AL registers to a value of 25. When the CTM value (TM0DH/TM0DL) matches the TM0AH/TM0AL value a CCRA interrupt will be generated, the CTM will generate a 100us interrupt.
  • Enable EMI, the CCRA interrupt enable bit T0AE, and the corresponding multi-function interrupt bit MF0E.
  • Enable the timer/counter to allow the timer to run. When the T0ON bit changes from low to high, the timer/counter registers (TM0DH/TM0DL) will be cleared to 00 automatically.
  • The CTM starts counting from 0. After 25 clocks, the value will match the CCRA register (TM0AH/TM0AL) value and generate a timer/counter interrupt with a 25x4=100us period.
  • In the compare match output mode, the CTM will provide two pins (TP0_0/TP0_1) for pulse outputs. The pulse outputs can be from TP0_0 or TP0_1 or from both TP0_0 and TP0_1 at the same time.
    Set the T0CP1/T0CP0 of the TMPC0 to 1, and then the CTM will be able to output pulses from both TP0_1/TP0_0 simultaneously.
  • Clear the TP00PS bit in PRM2 to 0, to setup the P0_0 output pin as PA0. When setting the TP00PS bit in PRM2 to 1, the TP0_0 output pin will be PC6. Here the I/O register whose I/O uses a common pin with TP0_0 can control the TP0_0 output to be inverted or not. Clearing the TP01PS bit in PRM2 to 0 and TP0_1 output pin will be PC5. When setting the TP01PS bit in PRM2 to 1, the TP0_1 output pin will be PD5. Here the I/O register whose I/O is using the common pin with TP0_1 can control the TP0_1 output to be inverted or not.
After the above setups, when the timer/counter counts from 0 to the CCRA value, the main counter will be cleared to 0 and generate a T0AF interrupt. The signal on the CTM output pin can generate a 1:1 square waveform.

Question 4

How do I send from the CTM output pin a PWM signal of 512us period with an adjustable duty ratio?

Answer

Take the HT66F40 as the example:

  • Firstly set the T0M1/T0M0 bits in TM0C1 to 10, namely set the CTM to the PWM mode.
  • Then set the T0IO1/T0IO0 bits in TM0C1 to 10, namely setup the CTM output pins as PWM outputs.
  • Set the T0OC bit in TM0C1 to 1, then the PWM outputs of the CTM will have Active High outputs.
  • Clear the T0DPX bit in TM0C1 to 0, then the CCRA value will control the duty and the CCRP value will control the period.
  • Set the high frequency system clock as an external 4MHz crystal oscillator by choosing fH as XTAL from the configuration options.
    Set the T0CK2~T0CK0 bits in TM0C0 as 010 to enable the CTM clock as fH/16, namely the 4MHz/16=250KHz with a clock cycle of 4us.
  • Set the CCRP value as 001, then the PWM period will be 128*4us=512us.
  • The PWM Duty can be controlled by the value in the CCRA register (TM0AH/TM0AL.)
  • Enable the EMI, CCRA interrupt enable bit T0AE, CCRP interrupt enable bit T0PE, and the corresponding multi-function interrupt bit MF0E.
  • Setup the timer/counter to have a timer function. When the T0ON bit changes from low to high, the timer/counter (TM0DH/TM0DL) value will be cleared to 00.
    When the main counter value matches the CCRA value, a T0AF interrupt will occur. When the main counter value matches the CCRP value, the T0PF interrupt will occur while the main counter will be cleared to 0 simultaneously.
  • In the PWM output mode, the CTM provides two pins (TP0_0/TP0_1) as PWM pulse outputs. The PWM pulse can be output from TP0_0 or TP0_1 or from both TP0_0and TP0_1 at the same time.
    Set the T0CP1/T0CP0 bits in TMPC0 to 1, then the CTM will be able to send the PWM signal from the TP0_1/TP0_0 output pin at the same time.
  • When bit0 (TP00PS) of PPM2 is cleared to 0, the TP0_0 output pin will be PA0. If bit0 (TP00PS) of PRM2 is set to 1, the TP0_0 output pin will be PC6. Here the I/O register whose I/O uses the pin common to TP0_0 can control the TP0_0 output to be an inverse value or not.
    When bit1 (TP01PS) of PPM2 is cleared to 0, the TP0_1 output pin will be PC5. If bit1 (TP01PS) of PRM2 is set to 1, the TP0_1 output pin will be PD5. Here the I/O register whose I/O uses the pin common to TP0_1 can control the TP0_1 output to be inverted or not.
After the above steps are implemented, the CTM will send out PWM pulses from the PWM output pin with a period of 512us. The PWM duty will be determined by the CCRA register.

Question 5

How does the STM generate a single pulse?

Answer

Take the HT66F40 as an example:

  • First set the T2M1/T2M0 bits in TM2C1 to 10, namely setup the STM to be in the PWM or single pulse mode.
  • Set T2IO1/T2IO0 in TM2C1 to 11, namely setup the STM output pin as a single pulse output.
  • Set the T2OC bit in TM2C1 to 1, and the STM will output a single Active High pulse.
  • Set the high frequency clock as an external 4MHz crystal oscillator by selecting fH as a XTAL using the configuration options.
    Set Bit6~Bit4:T2CK2~T2CK0 of TM2C0 to 010 to enable the STM clock as fH/16, namely 4MHz/16=250KHz with a 4us period.
  • Setup the CCRA value. The CCRA value x 4us will be the single output pulse width value.
  • Enable EMI, the CCRA interrupt enable bit T2AE, and the corresponding multi-function interrupt bit MF0E.
  • In the single pulse output mode, the STM can provide two pins (TP2_0/TP2_1) for the pulse output. The pulse output can be selected from TP2_0 or TP2_1 or from both TP2_0 and TP2_1 at the same time.
    Set T2CP1/T2CP0 of TMPC1 to 1, and then the STM will be able to the output a single pulse both from the TP2_0/TP2_1 pins at the same time.
  • When the TP20PS bit in PRM2 is cleared to 0, the TP2_0 output pin will be PC3. When the TP20PS of the PRM2 is set to 1, the TP2_0 output pin will be PD1.
  • When the TP21PS bit in PRM2 is cleared to 0, the TP2_1 output pin will be PC4. When the TP21PS bit in PRM2 is set to 1, the TP2_1 output pin will be PD4.
    After the above steps are implemented, the STM can send a single pulse from its output pin.
The pulse width will be determined by the CCRA register value.
  • The leading edge signal generated by the Single Pulse can be controlled by software by changing the T2ON bit from Low to High or from the TCK2 trigger impulse input. When the single pulse is active, T2ON should remain high. Once the T2ON bit has changed from high to low, the trailing edge of the single pulse will be generated. When the main counter value matches the TM2 value of the CCRA register, the T2ON bit will change from high to low and then generate a trailing edge of the single pulse. Therefore the TM2 value of the CCRA register will determine the width of the single pulse as shown as the figure below.

Question 6

How does the STM execute high pulse width detection?

Answer

Taking the HT66F40 as an example:

  • First set the T2M1/T2M0 bits in TM2C1 to 01, namely the STM will be placed in the capture input mode.
  • Set the T2IO1/T2IO0 bits of TM2C1 to 10, which will allow both rising edge and falling edges from the STM input pin to generate interrupts.
  • Set the high frequency clock as the external 4MHz crystal oscillator by selecting fH as a XTAL from the configuration options.
    Set the T2CK2~T2CK0 bits in TM2C0 as 010 to enable the STM clock as fH/16, namely 4MHz/16=250KHz with a 4us clock cycle.
  • Enable the EMI, CCRA interrupt enable bits T2AE and CCRP, the interrupt enable bit T2PE, and the corresponding multi-function interrupt bit MF0E.
  • In the capture input mode, the STM can provide two pin (TP2_0/TP2_1) as pulse inputs. The pulse inputs can be selected either from either TP2_0 or TP2_1.
    Set the T2CP1 or T2CP0 bits in TMPC1 as 1, which will allow the STM to choose the input pulse from the TP2_0 or TP2_1 pin.
  • When the TP20PS bit in PRM2 is cleared to 0, the TP2_0 input pin will be PC3. When the TP20PS bit in PRM2 is set to 1, the TP2_0 input pin will be PD1.
    When the TP21PS bit in PRM2 is cleared to 0, the TP2_1 input pin will be PC4. When the TP21PS bit in PRM2 is set to 1, the PT2_1 input pin will be PD4.
  • Set the TM2RP Register value as 00H, and choose the largest value of cycle overflow (65536 clock cycles.) Each timer/counter overflow will generate a CCRP interrupt. The pulse width can be measured by the interrupt numbers.
  • Enable the timer/counter to execute the timer operation, namely to set the T2ON bit from low to high to enable the main counter.
  • Input a high voltage pulse to the PC3 pin.
  • When a T2AF interrupt occurs during a rising edge, the CCRA value will be saved to CCRA_BANK1.
    When a T2AF interrupt occurs again during a falling edge, the CCRA value will be saved to CCRA_BANK2.
    When the pulse width is very long, some CCRP interrupts may occur between the rising and falling edges.
    Thus the way to measure the pulse width is: [(65536*n+ CCRA_BAK2) - CCRA_BAK1]*STM clock cycles (4us.)

Question 7

How can high pulse width detection be implemented by the ETM using the CCRA TP1A as an input pin?

Answer

Taking the HT66F40 as an example:

  • Firstly set the T1AM1/T1AM0 bits in TM1C1 to 01, therefore placing the ETM into the capture input mode.
  • Set the T1AIO1/T1AIO0 bits in TM1C1 to 10, therefore the ETM TP1A capture input pin will be able to generate an interrupt both by rising edges and falling edges.
  • Set the external high frequency clock to a 4MHz crystal oscillator by choosing fH as the External Crystal Oscillator-XTAL from the configuration options.
    Set the T1CK2~T1CK0 bits in TM1C0 to 010 to enable the ETM clock as fH/16, namely 4MHz/16=250KHz with a 4us clock cycle.
  • Enable EMI and CCRA to enable T1AE. Enable the CCRP interrupt enable bit T1PE and its corresponding multi-function interrupt bit, MF1E.
  • For the ETM, in the capture input mode, the CCRA can provide one pulse input pin (TP1A.) Set the T1ACP0 bit in the TMPC0 register to 1 to enable the ETM CCRA input pin (TP1A.)
  • Set the TP1APS bit in PRM2 to 0, therefore the TP1A input pin will be PA1. Set the TP1APS bit in PRM2 to 1, therefore the TP1A input pin will be PC7.
  • Set CCRP0～CCRP2 to 000, and select the maximum cycle overflow which is 1024 clock cycles. Each timer/counter overflow will generate a CCRP interrupt, then the number of interrupts can be used to measure pulse width length.
  • Enable the Timer/Counter to by changing T1ON from low to high.
  • Input a high voltage pulse to the TP1A pin.
  • When a T2AF interrupt occurs during a rising edge pulse, the CCRA value will be saved to CCRA_BANK1.
    When a T2AF interrupt occurs again during a falling edge pulse, the CCRA value will be saved to CCRA_BAK2.
    When the pulse width is large, some CCRP interrupts will occur between the rising and falling edges.
Therefore the way to measure the time of the pulse width is: [(1024*n+ CCRA_BAK2) - CCRA_BAK1]*STM clock cycle (4us.)
Now CCRB can also be used for pulse width detection.

Question 8

How does the single pulse generated by the ETM use the CCRA output pin?

Answer

Taking the HT66F40 as an example:

  • Firstly set the T1AM1/T1AM0 bits in TM1C1 to 10, therefore the ETM is in the PWM or single pulse output mode.
  • Set the T1AIO1/T1AIO0 bits in TM1C1 to 11, therefore the ETM output pin is setup as a single pulse output.
  • Set the T1AOC bits in TM1C1 to 1, therefore the ETM single pulse output is at an active level.
  • Set the external high frequency clock to a 4MHz crystal oscillator by choosing fH as the External Crystal Oscillator-XTAL from the configuration options.
    Set the T1CK2~T1CK0 bits in TM1C0 to 010 to enable the ETM clock as fH/16, namely 4MHz/16=250KHz with a 4us clock cycle.
  • Set the CCRA value. The width of the single pulse will be the value in the CCRA*4us.
  • Enable the EMI and CCRA interrupt enable bit T1AE. Enable the corresponding multi-function interrupt bit MF1E.
  • For the ETM, in the capture input mode, CCRA can provide one pulse input pin (TP1A.)
    Set the T1ACP0 bit in the TMPC0 register to 1 to enable the ETM CCRA input pin (TP1A.)
  • Set the TP1APS bit in PRM2 to 0, therefore the TP1A input pin will be PA1. Set the TP1A bit in PRM2 to 1, therefore the TP1A0 input pin will be PC7.
    After the above steps are implemented, the ETM can send a single pulse from its output pin.
The pulse width will be determined by the CCRA register value.
  • The leading edge signal can be generated by the single pulse as set by the T1ON bit with software control from low to high or triggered by the TCK1 input pulse. T1ON must remain high when the single pulse is being generated. Once the T1ON bit changes from high to low, the trailing edge of the single pulse will be generated. Therefore the value in the CCRA register of the TM1 will decide the pulse width. See the below figure for reference.

Question 9

How do I disable the comparator interrupt wake-up function when the device is powered-down?

Answer

As is the case with the other interrupt functions, the MCU will be woken up when the comparator interrupt value changes from 0 to 1. To avoid this set the interrupt flag to 1 before the device is Powered-down so that the interrupt will not wake up the MCU.

Question 10

How is the shared RESET and I/O pin used ?

Answer

The RESET pin is shared with the PB.0 port. The choice as to which function is used is selected using a configuration option. The pull-high options remain valid for this pin.

Question 11

How do I switch from Slow Mode to Normal Mode? What points should be noted?

Answer

In the Slow Mode, when the system is using the LXT or LIRC low speed oscillator and wants to switch to the Normal Mode and use a high speed oscillator, there are two ways of doing this:

  1. Set the HLCLK bit in the SMOD register to 1
  2. Set the CKS2~CKS0 bits to 010, 011, 100, 101, 110 or 111 when the HLCLK bit in the SMOD register bit is 0.
When switching modes from Slow to Normal, beware that the high speed oscillator will need a certain amount time to stabilise. Whether the oscillator is stable or not can be checked by examining the HTO bit in the SMOD register. As for how long it takes to stabilise depends on the oscillator types, crystal oscillator or RC oscillator.

Question 12

How does the device enter Sleep0 Mode? What features does Sleep0 Mode have?

Answer

When the IDLEN bit is cleared to 0 and the WDT or LVD is Off, the Sleep0 mode will a HALT instruction is executed.
Sleep0 Mode Features

  1. The system clock, WDT clock and TimeBase clock will be stopped. Also the application program will also stop running when the HALT instruction is executed.
  2. The RAM Data Memory and the internal register status will remain unchanged.
  3. In the Sleep0 Mode, if the WDT clock is selected as Fsub and being disabled, the WDT function will be stopped.
    If the WDT clock is selected as Fs system clock, the system clock will be stopped in Sleep0 Mode and also does the WDT clock source.
  4. In Sleep0 status, the I/O port status will remain unchanged.
  5. In the status register, the Power Down flag PDF will be set to 1 and the WDT overflow flag TO will be cleared as 0.

Question 13

How does the device enter Sleep1 Mode? What features does it have?

Answer When the IDLEN bit is cleared to 0 and the WDT is ON, Sleep1 mode will be entered when a HALT instruction is executed.
Sleep1 Mode Features

  1. The system clock and TimeBase clock will be stopped, also the application program will stop running when a HALT instruction is executed. The WDT will keep operating as its clock source comes from the Fsub clock.
  2. The RAM Data Memory and internal register contents will remain unchanged.
  3. The WDT will be cleared and restart counting as its Fsub clock source is enabled.
  4. In the Sleep1 mode, the I/O ports will remain unchanged.
  5. In the status register, the Power Down flag PDF will be set to 1 and the WDT overflow flag TO will be cleared to 0.

Question 14

How does the device enter the IDLE0 Mode? What features does it have?

Answer

When the IDLEN bit is set to 1 and the Fsyson bit is cleared to 0, the IDLE0 mode will be entered when a HALT instruction is executed.
IDLE0 Mode Features

  1. The system clock will be stopped, also the application program will stop running when a HALT instruction is executed. However the TimeBase and Fsub clock sources will keep operating.
  2. The RAM Data Memory and the internal register conditions remain unchanged.
  3. In the IDLE0 mode, if the WDT is enabled and uses Fsub as its clock source, the WDT will be cleared and restart counting. If the WDT clock source is fsys, the WDT will stop running.
  4. In the IDLE0 mode, the I/O port will remain unchanged.
  5. In the status register, the Power Down flag PDF will be set to 1 and the WDT overflow flag TO will be cleared.

Question 15

How do I enter IDLE1 Mode? What features does it have?

Answer

When the IDLEN bit is set to 1 and the Fsyson bit is set to 1, the IDLE1 mode will be entered when the HALT instruction is executed.
Features of the IDLE1 Mode:

  1. In the IDLE1 Mode, the system clock, TimeBase, and Fsub clock will keep operating, however the application program will stop running when a HALT instruction is executed.
  2. The RAM Data Memory data and the internal register status remain unchanged.
  3. In the IDLE1 status, the I/O ports will remain unchanged.
  4. In the status register, the Power Down flag PDF will be set to 1 and the WDT overflow flag TO will be cleared.

Question 16

When the configuration options select two instructions to clear the WDT, how is this used in the application program?

Answer

When the CLR WDT1 and CLR WDT2 instructions are selected from the configuration options, the WDT will be cleared by executing the instructions alternately. This method of using two instructions can be used to enhance noise immunity. The instructions can be located for example, into two main loops. One loop can contain the CLR WDT1 instruction and another can contain the CLR WDT2 instruction. Once a program error occurs, perhaps due to noise interference, that makes either loop unable to execute the CLR WDT1 and CLR WDT2 instructions, the WDT will overflow and reset the MCU.

Question 17

How is the TimeBase used?

Answer

The HT66Fxx series has two types of TimeBase which require clock selection and interrupt setup. From the figure below, the clock can be selected to be either Ftbc or fsys/4 using the Configuration Options, and then further clock division choices made using the TB02~TB00 or TB11~TB10 bits.
The TimeBase setup time is determined using interrupts. The interrupt enable bit of TimeBase0 and TimeBase1 is TB0E and TB1E. The interrupt status flag is TB0F and TB1F which will generate an interrupt vector such as at 24H and 28H or 34H and 38H for HT66F60.

Question 18

Which wake-up source can wake-up the system after it enters the Sleep or Idle Mode? How will the program run after the system is woken up?

Answer

The following wake-up sources exist:

  • An external pin reset
  • A falling edge on Port A
  • A system interrupt
  • A WDT Overflow
Each wake-up source has an influence on the program after the system wakes-up:
  • After the system is woken up by an external pin reset or a WDT overflow, the program will operate as if a reset had occurred. An external Pin Reset will reset the whole system while a WDT Overflow Reset only resets the event counter and stack pointer.
  • After the system is woken-up by a Port A pin, the program will continue operation from the instruction following the HALT instruction.
    1. If the system is woken up by an interrupt, the program can continue operation with two conditions:
      1. In the condition where the interrupt is not enabled or the stack is full, the program will continue operation from the instruction following the HALT instruction. The interrupt service routine will not be executed in this condition. Note that an interrupt wake-up is triggered by the interrupt request flag only, the interrupt enable bit has no influence over the interrupt wake-up function.

    2. The other condition is where the interrupt is enabled and the stack is not full. Here the program will first execute the interrupt service routine after being woken up by the interrupt.
      Before entering the Sleep or Idle mode, if the interrupt request flag is set to 1, then the corresponding interrupt wake-up function will be disabled.
A Port A Wake-up means that a falling edge on a PA pin has woken up the system. If a certain PA pin is already at a low level before entering the Sleep or Idle Mode, then this PA pin cannot wake-up the system.

Question 19

What voltage options are supported by the LVD? How are they selected?

Answer

There are eight voltage options. The LVD voltage options are selected u sing the VLVD0~VLVD2 bits (LVDC.2~LVDC.0) in the LVDC register as shown in the table.

Question 20

How do I know if the power supply voltage is lower than the LVD setup voltage?

Answer

There are two methods to check if the power supply voltage is lower than the LVD voltage:
Using a look up method: when the power supply voltage VDD is lower than the LVD setup voltage, the LDO bit in the LVDC register will be set to 1.
Using an interrupt method: the LVD has its own interrupt which is included in the multi-function interrupts. Only if the MF3E or MF5E bit (for the HT66F60), LVE and EMI bits are all set to 1 and a low voltage is detected by the LVD, will the program jump to the LVD interrupt vector address and the related interrupt routine serviced. When the LVD interrupt enters the interrupt service subroutine, the multi-function interrupt request flags MF3F or MF5F (for the HT66F60) and EMI will automatically be cleared to 0 while the LVF flag has to be cleared using the application program. Otherwise the LVF flag will remain at a high level when the program returns from the LVD interrupt routine.

Question 21

How is the power consumption affected when the LVR/LVD is enabled?

Answer

For the Enhanced A/D Flash series of MCUs, enabling the LVR or LVD functions will consume additional power. When the LVR is disabled and LVDEN=1, about 75uA~115uA of additional current is used. When the LVR is enabled and LVDEN=1, about 90uA~135uA of additional current is required. When the LVR is enabled and LVDEN=0, about 60uA~90uA of additional current is required. Note that for battery powered applications, it is recommended to disable the LVD before entering the Sleep Mode to reduce power consumption. The LVD can be restarted depending on the actual requirements after wake-up.

Question 22

How do I disable the LVD Wake-up function?

Answer

When the MCU enters the Power Down Mode, if the LVDEN bit is high, which means the low voltage detector is operating, then if the power supply voltage is detected to be lower than the LVD voltage, the LVF flag will be set and an interrupt will be generated. This will then wake up the device if it is powered down. If the MCU wake-up is not required, then the LVF flag should first set high before the device is powered-down.

Question 23

How do I enable the LXT quick start function in the HT66F40?

Answer

Clear LXTLP in the TBC register as 0 to enable the quick start function of the external 32768Hz crystal oscillator. Set the LXTLP bit in the TBC register to 1 after a quick start operation to allow the oscillator to run in its low power mode to conserve power.

Question 24

How can the device switch from the Normal Mode to the Slow Mode? Are there any special points to note?

Answer

When the system operates in the Normal Mode, more power will be consumed. Clear the HLCLK bit in the SMOD register from 1 to 0, and set bits CKS2~CKS0 (SMOD.7~SMOD.5) as 000 or 001 to enable the system to switch to the Slow Mode so as to save power. When the system switches from Normal to Slow Mode, the high speed clock will be disabled automatically. Take care when in this condition as it will also stop clock sources such as fH, fH /2, fH /4, fH /8, fH /16, fH /32, fH /64 and affect some internal functions such as the TMs, SIM etc. If any of these clocks are used by other functions then the relevant function will also be disabled.

Question 25

In the HT66/68 series of MCUs, why, when using the PB2/OSC2 pin as an output pin to drive an LED, when the application circuit is powered on, the PB2/OSC2 pin will output a low level and then a high level, causing the LED to flash?

Answer

When an HT66/68 series MCU is in the Power On Reset status, the default pin-shared function of the PB1/OSC1 and PB2/OSC2 is for the high speed oscillator, HXT, for which the logic condition of the PB1/OSC1 and PB2/OSC2 pins is reversed. For example, if the PB1/OSC1 pin of the application circuit is connected to a high level, then the PB2/OSC2 pin will be at a low level until the reset has finished. Only then will the desired function as specified by the configuration options be setup.

Question 26

How do I manage the occasional condition of SCL being locked a low level while using the I2C (Slave) function in the HT66/68 series of MCUs?

Answer

1. It is suggested that the I2C debounce time be set to 2 or 4 system clocks using the Configuration Options to avoid the I2C Bus from being influenced by noise and causing erroneous operation. For the I2C De-bounce time reference and the I2C Bus speed supported by the MCU system frequency, refer to the table below:

2. Check if the control timing of the I2C Master meets with the I2C specifications.

Question 27

What can I do if the SDA pin has no signal output when using the I2C (Slave) function in the HT66/68 series of MCUs?

Answer

Check if the SDA pin has been properly connected to a pull-high resistor. This is because the I2C Bus is an open-drain structure, requiring the SCL/SDA lines to be connected to a pull-high resistor.

Question 28

Why is it not possible to write low byte data into the timer register while using the Timer in the HT66/68 series of MCUs?

Answer

When writing the low byte data, the hardware will first place the data first into a temporary buffer. Then a high byte data write must be executed to transfer the high and low byte data into the actual timer registers. The low byte data will not be written to the timer register if this order is not followed. The Timer should first write the low byte and then execute a high byte write to correctly write data to the timer registers.

Question 29

What is the reason for bad data reception while using the UART function in the HT66FU/68FU series of MCUs? How do I handle this?

Answer

A bad data reception may occur resulting from the error between the actual and expected Baud Rate values, created when setting the serial communication speed. The Baud Rate of the UART serial communication speed should be within ±5％, which is the total of the clock frequency error plus the dividing error of the Baud Rate Generator. Therefore, to improve bad reception conditions, it is necessary to check the Baud Rate value of the serial communication speed.


Points to Note

 

Question 1

How do I select the WDT clock? Are there any special points to note?

Answer

There are three types of clock sources for the WDT. These are fRTC, fLIRC or fSYS /4. The clock fS can be selected from the configuration options. Additionally, WS2~WS0 in the WDTC register can implement further clock division: 2^8~2^15 of the clock fs.
Notes for WDT clock selection:
When the WDT clock fS is selected as fSYS/4, when the IDLE0 or SLEEP Mode is entered the WDT will be stopped. When the system operates in high noise environments, selecting the WDT clock fS as fSUB is recommended. Otherwise the WDT is disabled only when the WDT Disable is selected from the configuration option and the WDTEN3~0 bits are set to 1010b. If WDT Enable is selected or the WDTEN3~0 bits have any other value, then it will not be possible to disable the WDT.

Question 2

How do I use the interrupt function? What difference are there between a Multi-function Interrupt and a normal Interrupt?

Answer

Notes for using interrupts:
In addition to the interrupt enable bit of the corresponding interrupt source, the master interrupt EMI bit should be enabled. Only when no stack overflow has occurred can an interrupt can be generated.
Regarding the difference between a Multi-function interrupt and a general interrupt, note that the multi-function vector is shared by more than one interrupt source. After an interrupt occurs and the interrupt is serviced, only the multi-function interrupt flag will be cleared automatically. The interrupt flags of the corresponding interrupt sources that share this common multi-function interrupt vector, will not be cleared automatically. As a result they need to be cleared by the application program. In this way the interrupt which generated the multi-function interrupt can be located.

Question 3

What is the I/O status after a HALT instruction is executed? With regard to the I/O pins are there any special points to note before the HALT instruction is executed?

Answer

After a HALT instruction is executed, any input pins will remain in a high impedance condition and any output pins will remain at their present logical status. To minimise power consumption in the power-down condition, the input pins must be properly taken care of, by preventing them from being in a floating condition.

Question 4

What special points should be noted for each TM operating in the Timer/Counter Mode in the HT66F40?

Answer

The TM Timer/Counter Mode is the simplest mode and has no output signals. Each corresponding output pin for the TM should be disabled.

Question 5

When the operating mode of the TM is changed what special points should be noted?

Answer

To ensure reliable operation of the TM, it should first be disabled before changing operating modes.