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Functional Description
Question 1
How many PWM outputs are there on the HT45FM03B?
Answer
The HT45FM03B provides six PWM outputs, the PWM0H, PWM0L, PWM1H, PWM1L, PWM2H, and PWM2L. Complementary output pair settings are also available such as PWM0H with PWM0L, PWM1H with PWM1L, and PWM2H with PWM2L.
Question 2
How do I set the PWM to either Active High or Active Low?
Answer
From the Configuration Options section in the Tools Menu of the IDE3000:
1. In the PWMLEV option, select the PWMxH output as Active High or Active Low.
2. In the PWMCLEV option, select the PWMxL output as Active High or Active Low.
Question 3
How can I set the PWM resolution to (8+2) bit?
Answer
From the Configuration Options section in the Tools Menu of the IDE3000, select the PWM Mode to be (8+2) Mode.
Question 4
How do I set the PWM frequency? Can I setup three pairs with different frequencies?
Answer
This can be done by programming bits PWMPS2~PWMPS0 in the PWMC1 register. For details see the datasheet. All six PWM outputs must share the same frequency - individual frequency settings are not allowed.
Question 5
How do I setup the PWM Duty Cycle? Is it possible to setup three different duty cycles for the PWM outputs?
Answer
1. Write the PWM Duty Cycle value respectively into the PWMxH and PWMxL registers. The Duty Cycle is setup individually for each PWM output pair. .
2. Choose the PWM Duty Mode from the Configuration Option section in the Tools Menu of the IDE3000 where three sets of PWM values with different or the same Duty Cycle are acceptable.
Question 6
How can the PC0, PC3, and PC5 pins be setup as PWM outputs?
Answer
1. Set PWMxH and PWMxL to either Active High or Active Low
2. Set the PWM Mode as 10 bit, (9+1) bit, (8+2) bit or (7+3) bit
3. Set the PWM frequency
4. Set Bit 0, Bit 3 and Bit 5 of the PCPWMC register to High meaning that the PC0, PC3 and PC5 pins will be setup in the PWM mode. Set the other bits to zero to setup the pins as I/O pins.
5. Set Bit 0, Bit 3 and Bit 5 of the PCPWMD register to High meaning that the outputs of WM0HD, PWM1LD, PWM2LD are PWM signals. Set the other bits to zero to setup the pins as I/O pins.
6. Set Bit 0 PWMEN in PWMC0 to Enable (High)
7. Set Bit 6 PWMCTRL in PWMC0 to Active (High)
8. Write the PWM Duty Cycle values separately to the PWMxH and PWMxL registers
9. Set the I/O control register bits PCC0, PCC3 and PCC5 to Low and the PC0, PC3, PC5 bits in the I/O register to High
Question 7
What is the PWM Buffer bit in the PCPWMC register used for?
Answer
It is used to:
1. When the PWMBUF bit is Low, this means that if the PWM Duty Cycle register value is renewed, then the current PWM Duty Cycle will be changed immediately
2. When the PWMBUF bit is High, this means that if the PWM Duty Cycle register is renewed, then the PWM Duty Cycle will not be changed until the present Duty Cycle has ended
Question 8
How do I set the PWM outputs to complementary outputs?
Answer
1. Set the PWMCEN bit in the PWMC0 register High, which means that PWMxH and PWMxL will be switched to complementary PWM outputs.
2. If Dead Time is required, set the DTEN bit in the PWMC0 register High, which means that the PWMxH and PWMxL complementary outputs will incorporate some Dead Time.
Question 9
How do I adjust the Dead Time length?
Answer
1. To adjust the Dead Time length and its relationship to the system frequency use bits DTPS1 and DTPS0 in the MISC register.
2. The PWMDT2~PWMDT0 bits in the PWMC0 register are used to setup the Dead Time length. For details please refer to the data sheet. All PWM outputs must have the same Dead Time. Individual value setting is not allowed.
Question 10
How can I generate a PWM interrupt?
Answer
Set the EPWMI bit in the INTC1 register to Enable (High) and the EMI in the INTC0 register to Enable (High) allow interrupts to be generated at every PWM rising edge.
Question 11
How can the PWM outputs be switched off?
Answer
1. To disable the PWM outputs, from the Configuration Option section in the Tools Menu in the IDE3000, choose the Comparator Interrupt Source as PA3 Falling Edge or the Comparator Output Falling Edge.
2. Setup the PWMSP2~PWMSP0 bits in the PWMC1 register to determine which condition is to disable or enable the PWM outputs. Details as follows.:
PWMSP2~PWMSP0 |
Description |
000 |
Disable or enable the PWM with the users program. |
001 |
Disable the PWM when the comparator output generates a falling edge or the PA3 input produces a falling edge. |
010 |
Disable the PWM when the external interrupt 1 generates an interrupt. |
011 |
Disable the PWM when the comparator output generates a falling edge or the PA3 input produces a falling edge or the external interrupt 1 generates an interrupt. |
100 |
- When the comparator output generates a falling edge or the PA3 input produces a falling edge, make the PWMxH outputs Inactive and the PWMxL outputs Active.
- When the comparator output generates a falling edge or the PA3 input produces a falling edge, the PWM will return to the same status before being triggered.
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PWMSP2~PWMSP0 |
Description |
101 |
- When the comparator output generates a falling edge or the PA3 input produces a falling edge, make the PWMxH outputs Inactive and the PWMxL remains a PWM output.
- When the comparator output generates a falling edge or the PA3 input produces a falling edge, the PWMxH return to the status before it was triggered.
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110 |
When the comparator output generates a falling edge or the PA3 input produces a falling edge, make the PWMxH outputs Inactive and the PWMxL remains PWM output. |
111 |
When the comparator output generates a falling edge or the PA3 input produces a falling edge, make the PWMxH outputs Inactive and the PWMxL outputs Active. |
Question 12
How do I enable an ADC conversion when a PWM interrupt occurs?
Answer
1. Set the EPWMI bit in the INTC1 register to Enable (High) and the EMI bit in the INTC0 register to Enable (High) to generate interrupts on every PWM falling edge
2. Set the PWMTAD bit in the PWMC2 register to Enable (High)
3. A conversion should be started after a PWM interrupt occurs and after three ADC clock periods have occurred. After an ADC conversion, the digitised analog signal voltage can be retrieved from the ADRH and ADRL registers.
Question 13
What is the BLDCMD bit in the DBTC register for?
Answer
In the BLDC motor applications, it is possible that both the high and low drive signals are PWM signals. It is also possible that only the high drive signal is a PWM and the low drive signal is an I/O line with a high or low level. In this latter case, in order to prevent both high and low drive conduction at the same time (due to program switching), the BLDCMD bit can be Enabled (High) to stop a simultaneous connection. This hardware bit always has priority over software switching.
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