HT82A824R -- USB Audio MCU (Restricted Products)
 

General Description

This HT82A824R is an 8-bit high performance RISC microcontroller designed for USB Speaker related product applications. The HT82A824R combines a 16-bit DAC, USB transceiver, SIE (Serial Interface Engine), audio class processing unit, FIFO, 8-bit MCU into a single chip. The Sigma-Delta DAC in the HT82A824R is operating at the 48kHz or 44.1kHz sampling rate. The HT82A824R has a digital programmable gain amplifier. The gain range is from -32dB to +6dB. The external stereo audio input can be the other source of power amplifier by software control.

The HT82A824R has a Human Interface Device function that allows a user to control the playback volume at the device side. The HT82A824R also can mute the analog output signal by the operation of HID buttons.
 

Features

CPU Features

  • USB 2.0 Full Speed Compatible
  • USB spec V1.1 full speed operation and USB audio device class spec V1.0
  • Operating voltage at fSYS = 6M/12MHz: 4.0V~5.5V
  • 48KHz/44.1KHz sampling rate for audio playback selected by software
  • Embedded class AB power amplifier for ear phone speaker driving (32Ω)×2
  • Embedded High Performance 16-bit stereo audio Sigma-Delta DAC
  • Pass Microsoft® DTM (WHQL) USB audio device
  • Audio playback digital volume control
  • 6 endpoints supported including endpoint 0
  • Support 1 Control, 2 Interrupts, 1 Isochronous and 2 Bulk transfers
  • One hardware implemented Isochronous transfer
  • Total FIFO size are 528 bytes (8, 8, 384, 32, 32, 64 for EP0~EP2,EP4~EP6)
  • 8192×16 Program Memory
  • 352×8 MCU type data memory RAM (Bank 0, Bank 9)
  • 128×8×4 Speaker Output Data or 12-bit ADC Converted Data RAM (Bank1, Bank2, Bank3, Bank4)
  • USB Audio and 12-bit ADC Stereo Data Capture DMA
  • 128×8×4 MCU Type General Purpose Data RAM (Bank5, Bank6, Bank7, Bank8)
  • 6-channel 12-bit A/D converter
  • 2-channel PWM function shared with PB2~PB3
  • Dual Programmable Attenuator for 2-channel external stereo audio input
  • Universal Asynchronous Receiver Transmitter (UART) shared with PB0~PB1
  • SPI interface (master and slave mode) shared with PC4~PC7
  • Programmable frequency divider (PFD) function shared with PC0
  • Power-down function and wake-up reduce power consumption
  • Up to 21 bidirectional I/O lines
  • Dual 16-bit programmable Timer/Event Counters with overflow interrupts
  • Watchdog Timer
  • 16-level subroutine nesting
  • Bit manipulation instruction
  • 16-bit table read instruction
  • 63 powerful instructions.
  • All instructions executed within one or two machine cycles
  • Low voltage reset function((3.0V±0.3V)
  • 48-pin LQFP package

Technical Document

Other Information