Holtek's new generation Touch Key Flash series MCUs are fully integrated with touch key functions, communication interfaces and display functions thus reducing greatly the need for external components. With the features of high S/N ratio touch switch control, power fluctuation rejection and excellent noise immunity, the stability of these touch keys has been greatly improved, thus offering solutions over traditional mechanical keys with their inherent weakness of rapid wear and tear and manufacturing complexity. These features combine to ensure effective and rapid product development in areas such as household appliances and other touch key controlled products.
- What is the difference between the EEPROM data register, the special internal function register and the general registers?
- What are the EEPROM read and write times of the BS83/84XXXA series and how many read and write operations do the MCUs support?
What development tools are provided for the BS83/84XXXA series of MCUs?
Refer to the following table based on the Item No.
- Touch Key Development Kit
- e-Link (for Touch)
- Isolation Board
- HEX Editor
Users can choose the tools required (refer to BS83/84XXXA TouchLib) to develop programs according to their required specifications.
How do I manage touch input pins that are not used?
It is recommended that they are setup as outputs with no loads connected.
What is the I²C communication frequency of the BS83/84XXXA series of MCUs?
Is it acceptable to execute a CALL instruction during an interrupt service routine?
For the reason that the stack number in the BS83Bxx Flash devices is limited, care must be taken when executing the CALL instruction in an interrupt. If the stack is full when entering an interrupt, a stack overflow will occur if a CALL is executed which will corrupt the program flow and render an interrupt return unsuccessful. Therefore, using the CALL within an interrupt routine must be very carefully managed especially ensuring that spare stack levels are available.
Is it acceptable to allow a similar interrupt to occur when one is already being serviced?
Theoretically, when entering an interrupt routine the MCU will automatically clear the EMI flag (EMI=0), and forbid all other interrupts to be generated. If the EMI bit however is manually set high using the application program after the interrupt routine is entered , then any other interrupts (including the same interrupt) can be generated again when the stack is not full. To allow the same interrupt to be repeatedly generated, then care must be taken to backup data to prevent it being corrupted by subsequent interrupts.
How do I back up the interrupt data without using Push and POP instructions?
Without Push and POP instructions, designers can still assign special memory RAM Byte (ex. db ACCStack; for ACC Storage) to store data which may be corrupted during an interrupt. First save the ACC to the a memory register and then use ACC to move backup the status register and other data by also saving it to other data memory registers. Before returning from the interrupt, restore the backed updata in reverse order and finally execute the RETI instruction to return to the main program.
What points should be noted when using the table read instruction?
There are two table read instructions. One is TABRDC for reading the table data in the present program memory page, and the other is TABRDL for reading data from the last page of the program memory. The Low Address of the table must be first written to the TBLP register before executing the table read instruction. The Low Byte Data of the table will be stored in the register assigned by the instruction while the High Byte Data will be stored in TBLH. Note that unused high address bits must be written as zero.
What is the difference between the EEPROM data register, the special internal function register and the general registers?
The internal special function register uses direct addressing while the general registers can use either direct addressing or indirect addressing via the indirect pointer (MP0, MP1) for access. As for the EEPROM data register, which is quite different from the above two kinds, it needs to use the control register EECR (40H) in the BANK 1 to execute indirect addressing access.
EEPROM Register List
For the EEPROM register description, refer to the BS83Bxx datasheet.
What format is data format of the data when accessing the internal EEPROM?
The data is MSB format, which means most significant bit first, for all transmission. Information, including Instruction Code, Address, Data, are all transmitted using MSB when an SK rising edge occurs.
How do I calculate the WDT time out period?
WS2,WS1,WS0: WDT time-out period selection
These three bits determine the division ratio of the Watch dog Timer source clock, which in turn determines the time out period.
What is the clock source for the WDT?
There is only one clock source for the WDT and that is the LIRC oscillator.
How many SIM operating modes do the BS83/84XXXA series support?
Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fLIRC
101: SPI slave mode
110: I2C slave mode
What is the current consumption of the BS83/84XXXA series?
There are five different modes of operation for the BS83/84XXXA MCUs, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the MCU, the NORMAL mode and SLOW mode. The remaining three modes, the SLEEP mode, IDLE0 and IDLE1 mode are used when the microcontroller CPU is switched off to conserve power.
What are the EEPROM read and write times of the BS83/84XXXA series and how many read and write operations do the MCUs support?
EEPROM data memory can undertake up to 1 million read and write operations.